High speed downlink packet access (HSDPA) has been introduced in Release 5 of the third generation partnership project (3GPP) standards. HSDPA requires additional uplink and downlink control signaling to support hybrid automatic repeat request (H-ARQ) and adaptive modulation and coding (AMC). AMC is a form of link adaptation wherein the modulation type, either QPSK or 16-QAM, and coding rate are chosen based on channel quality estimates reported by a wireless transmit/receive unit (WTRU).
One of the problems experienced in the operation of AMC and H-ARQ techniques is delay in the feedback loop. In order to resolve delay problems, the downlink control signaling, which is carried on a HS-SCCH, is staggered in time with respect to a high speed-downlink shared channel (HS-DSCH), which carries the bulk of the data. FIG. 1 shows a prior art timing relationship between the HS-SCCH and the HS-DSCH. Both the HS-SCCH and the HS-DSCH include a three time slot frame which is approximately two (2) milliseconds. One time slot is overlapped between the HS-SCCH and the HS-DSCH.
A HS-SCCH carries the following information: 1) channelization-code-set information; 2) modulation scheme information; 3) transport-block size information; 4) H-ARQ process information; 5) redundancy and constellation version; 6) new data indicator; and 7) WTRU identity. The channelization-code-set information and the modulation scheme information are time critical in configuring a receiver for demodulating data received through the HS-DSCH. This information must be demodulated or buffered prior to complete reception of the data via the HS-DSCH.
A cyclic redundancy check (CRC) is employed for a high degree of confidence in determining if the WTRU is scheduled for a HS-DSCH downlink. However, since the CRC is calculated based on the entire two (2) millisecond HS-SCCH sub-frame, the CRC cannot be used until the WTRU has received the entire HS-SCCH sub-frame, while the WTRU has already begun receiving data through the HS-DSCH.
The data received through the HS-DSCH may be simply buffered during every HS-SCCH sub-frame until the CRC can be verified, and then may be discarded in the event that the HS-SCCH is not directed to a particular WTRU. However, this approach has two major disadvantages. First, the power consumed for buffering the received data at chip rate for potential demodulation is significant. The WTRU has to consume power during all sub-frames, even though no HS-DSCH is scheduled for the WTRU. Second, there are strict timing requirements enforced on the decoding of the HS-DSCH in the WTRU which requires fast generation of an acknowledgment or negative-acknowledgement. The budget of time allotted for decoding the HS-DSCH is eroded by the additional buffering delay needed to utilize the HS-SCCH CRC in configuring a HS-DSCH demodulator.
Therefore, there is a need for a method and apparatus which provide faster detection of the HS-SCCH before receipt of data via the HS-DSCH.